A fast and area-efficiency BWC array D/A and A/D conversion scheme

Author

Singh, Rajinder ; Singh, S.P. ; Bhattacharyya, A.B.

Author_Institution

Centre for Appl. Res. in Electron., Indian Inst. of Technol., New Delhi, India

Volume

36

Issue

6

fYear

1989

fDate

6/1/1989 12:00:00 AM

Firstpage

912

Lastpage

916

Abstract

A modification to D/A and A/D converters of the charge redistribution type is suggested. It reduces the silicon area requirement by a factor of two or more (up to 6.5 for 8-bit converters) and increases the speed by a similar factor, while retaining compatibility to presently used MOS fabrication processes. The scheme is sufficiently insensitive to undercuts and parasitics. Under the scheme, some of the LSB (least-significant bit) side branch capacitors are realized as a series combination of unit capacitors and the higher-bit capacitances are adjusted to make them binary-weighted to the LSB capacitances. Simulation results and an implemented binary-weighted capacitor (BWC) scheme are shown

Keywords

MOS integrated circuits; analogue-digital conversion; digital-analogue conversion; A/D conversion scheme; ADC; D/A convertors; DAC; LSB side branch capacitors; MOS fabrication processes; area-efficiency BWC array; binary-weighted capacitor; charge redistribution type; chip area-reduction; high speed operation; least-significant bit; Capacitors; Circuits; Fabrication; Laboratories; Large scale integration; Process design; Resistors; Silicon; Telephony; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.90417

Filename

90417