Title :
Binary counter with counting period of one half adder independent of counter size
Author :
Ercegovac, Milos ; Lang, Tomas
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fDate :
6/1/1989 12:00:00 AM
Abstract :
The properties that make a fast counter suitable for many applications are: (1) a high counting rate, independent of the counter size; (2) a binary output that can be read on-the-fly; (3) a sampling rate equal to the counting rate; and (4) a regular implementation suitable for VLSI. The authors describe the implementation of a counter having these properties. The minimum period of the counter is equal to the delay of one half adder plus the delay of loading a flip-flop. Both a modulo-2n case and the more general modulo-p cases are considered
Keywords :
VLSI; counting circuits; integrated logic circuits; VLSI; binary output; fast counter; logic circuits; modulo-2n case; modulo-p cases; Adders; Counting circuits; Economic forecasting; Flowcharts; Polynomials; Sampling methods; Signal processing algorithms; Speech processing; Symmetric matrices; Very large scale integration;
Journal_Title :
Circuits and Systems, IEEE Transactions on
