DocumentCode :
1442709
Title :
Automatic synthesis of equipment recipes from specified wafer-state transitions
Author :
Davis, Joseph C. ; Mozumder, Purnendu K. ; Burch, Richard ; Fernando, Chenjing ; Apte, Pushkar P. ; Saxena, Sharad ; Rao, Suraj ; Vasanth, Karthik
Author_Institution :
Adv. Technol. Center, Texas Instrum. Inc., Dallas, TX, USA
Volume :
11
Issue :
4
fYear :
1998
fDate :
11/1/1998 12:00:00 AM
Firstpage :
527
Lastpage :
536
Abstract :
Run-to-run and supervisory control algorithms determine the equipment recipe to produce a desired output wafer state given the incoming wafer state and the current equipment model. For simple, low-dimensional equipment models, this problem is not difficult. However, when there are multiple responses for the system and the equipment models are nonlinear, automated synthesis of recipes is complicated by the potential for multiple solutions. While there are standard techniques for handling such inverse problems in general, each of these techniques is optimal only under certain conditions. We present a framework for performing automated synthesis of recipes that integrates database search, local optimization, and global optimization into a consistent methodology that is applicable to a wide range of equipment models and inversion problems in general. The integrated framework imposes quasi-continuity on the extracted recipes, is scalable to systems of high dimensionality, and can be optimized to minimize the expected synthesis time for any given problem. The framework has been implemented in a system that performs statistical optimization of CMOS transistor designs. The integrated framework provides a factor of 16 increase in performance over global optimization and a factor of three increase over exhaustive search and multiple starts of a local optimizer
Keywords :
inverse problems; optimisation; process control; semiconductor process modelling; CMOS transistor design; automatic synthesis; database search; equipment recipe; inverse problem; nonlinear model; run-to-run control algorithm; semiconductor device; statistical optimization; supervisory control algorithm; wafer state transition; Control system synthesis; Databases; Design optimization; Geometry; Inverse problems; Optimization methods; Process control; Semiconductor device modeling; Space technology; Supervisory control;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/66.728548
Filename :
728548
Link To Document :
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