Title :
Simulating the impact of pattern-dependent poly-CD variation on circuit performance
Author :
Stine, Brian E. ; Boning, Duane S. ; Chung, James E. ; Ciplickas, Dennis J. ; Kibarian, John K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
fDate :
11/1/1998 12:00:00 AM
Abstract :
In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 μm 64×8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell
Keywords :
SRAM chips; semiconductor process modelling; 0.25 micron; SRAM macrocell layout; Si; circuit simulation; die-level polysilicon critical dimension variation; pattern-dependent poly-CD variation; signal skew; Circuit optimization; Circuit simulation; Design methodology; Gaussian distribution; Laboratories; MOS devices; Macrocell networks; Monte Carlo methods; Random access memory; Semiconductor device measurement;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
