DocumentCode :
1442784
Title :
An extraction method to determine interconnect parasitic parameters
Author :
Chao, Chuan-Jane ; Wong, Shyh-Chyi ; Chen, Ming-Jer ; Liew, Boon-Khim
Author_Institution :
Inst. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
11
Issue :
4
fYear :
1998
fDate :
11/1/1998 12:00:00 AM
Firstpage :
615
Lastpage :
623
Abstract :
Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement). In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of the same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer
Keywords :
VLSI; capacitance; failure analysis; integrated circuit interconnections; integrated circuit testing; network parameters; chemical-mechanical polished processes; circuit failure analysis; circuit speed; effective line width; extraction method; interconnect parasitic parameters; interlayer capacitances; intralayer capacitances; line resistance; nonglobal planarized processes; process development; process spread; ring oscillator speed; test patterns; Capacitors; Circuit synthesis; Condition monitoring; Data mining; Electrical resistance measurement; Failure analysis; Integrated circuit interconnections; Integrated circuit measurements; Parasitic capacitance; Testing;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/66.728559
Filename :
728559
Link To Document :
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