Title :
Measurement and characterization of multilayered interconnect capacitance for deep-submicron VLSI technology
Author :
Wee, Jae-Kyung ; Park, Young June ; Min, Hong Shick ; Cho, Dae-Hyung ; Seung, Man-Ho ; Park, Hun-Sup
Author_Institution :
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
fDate :
11/1/1998 12:00:00 AM
Abstract :
This paper presents the measurement and characterization of multilayered interconnect capacitances for a 0.35-μm CMOS logic technology, which become a critical circuit limitation to high performance VLSI design. To measure multilayered capacitances of nonstacked, stacked, and orthogonally crossing interconnect lines, new test structures and measurement methods are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies. This study shows that the calibration method considerably improves the accuracy of simulation results compared with measured results
Keywords :
CMOS logic circuits; VLSI; calibration; capacitance measurement; integrated circuit interconnections; integrated circuit measurement; integrated circuit testing; technology CAD (electronics); 0.35 micron; CMOS logic technology; TCAD tools; calibration method; critical circuit limitation; deep-submicron VLSI; high-speed interconnect technologies; multilayered interconnect capacitance; nonstacked interconnect lines; orthogonally crossing interconnect lines; stacked interconnect lines; test structures; CMOS logic circuits; CMOS technology; Capacitance measurement; Circuit simulation; Circuit testing; Electric variables measurement; Integrated circuit interconnections; Semiconductor device measurement; Tellurium; Very large scale integration;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
