Title :
Maximum likelihood estimation for failure analysis [IC yield]
Author :
Yu, Jianlin ; Ferguson, F. Joel
Author_Institution :
Design Autom. Group, Integrated Device Technol. Inc., Santa Clara, CA, USA
fDate :
11/1/1998 12:00:00 AM
Abstract :
This paper presents an iterative maximum likelihood (ML) estimation method for statistical analysis of yield loss. By means of inductive fault analysis (IFA) and circuit simulation, the mapping between defect types to the corresponding fault signature is constructed. Using the count of each fault signature occurrence, which is provided by a tester on defective ICs, the most likely causes of low yield are identified automatically without the need for physically deprocessing the defective IC´s. We present an experiment on an SRAM cell array to illustrate the effectiveness of the iterative ML algorithm
Keywords :
failure analysis; integrated circuit yield; iterative methods; maximum likelihood estimation; probability; IC manufacture; SRAM cell array; circuit simulation; defect types; defective ICs; failure analysis; fault signature; inductive fault analysis; iterative ML algorithm; iterative ML estimation method; maximum likelihood estimation; statistical analysis; yield loss; Automatic testing; Circuit analysis; Circuit faults; Circuit simulation; Circuit testing; Failure analysis; Iterative methods; Maximum likelihood estimation; Statistical analysis; Yield estimation;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
