Title :
Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design
Author :
Hamzaoglu, Fatih ; Wang, Yih ; Kolar, Pramod ; Wei, Liqiong ; Ng, Yong-Gee ; Bhattacharya, Uddalak ; Zhang, Kevin
Author_Institution :
Portland Technol. Dev., Intel, Hillsboro, OR, USA
Abstract :
Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes.
Keywords :
SRAM chips; embedded systems; low-power electronics; scaling circuits; SRAM scaling; bit cell optimizations; circuit techniques; embedded memory; low voltages; nanoscale SRAM design; robust operation; six-transistor SRAM cells; Circuit synthesis; Embedded systems; Memory; SRAM chips; SRAM; VCCmin; design and test; high-performance applications; low power; minimum operating voltage;
Journal_Title :
Design & Test of Computers, IEEE
