Title :
Modeling Process Variability in Scaled CMOS Technology
Author_Institution :
Univ. of Colorado, Colorado Springs, CO, USA
Abstract :
Process variability has become a critical issue in scaled CMOS design. This article provides a comprehensive view on the predominant variation sources in sub-90-nm devices, their impact on device and circuit performance, and various modeling approaches for statistical circuit analysis.
Keywords :
CMOS integrated circuits; network analysis; statistical analysis; circuit performance; complementary metal-oxide-semiconductor; device performance; modeling process variability; scaled CMOS design; scaled CMOS technology; statistical circuit analysis; CMOS process; CMOS technology; Circuit optimization; Circuit synthesis; Design methodology; Doping; MOSFET circuits; Power MOSFET; Semiconductor device modeling; Very large scale integration; compact variability modeling; design and test; gate-oxide thickness variability; high-k dielectric; line-edge roughness; metal gate; polysilicon granularity; process variability; random discrete dopants; scaled CMOS technology; statistical compact modeling;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2010.50
