A simple and efficient self-limiting erase scheme for high performance split-gate flash memory cells

This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells.