An Architecture for Implementation of IEEE1588v2 over MPLS/MPLS-TP Networks

IEEE 1588v2 has emerged as the prime candidate for synchronization of PSN (Packet Switched Network). It is an asynchronous protocol and operates on master-slave hierarchy. Telecom profile of 1588v2 i.e. ITU G.8275.x is under standardization and discussions for various aspects are underway. Similarly MPLS has been adopted as core transport technology for present PSN. In this paper implementation of IEEE 1588v2 on the top of MPLS/MPLS-TP have been considered. An alternate for the most important aspect of IEEE 1588v2 i.e. BMCA (Best Master Clock Algorithm) has been proposed after studying different prevailing algorithms. Presently, failure of master initiates re-election of a master which takes approximately 10 sync periods. During re-election period, all slaves in the system continue on their own and there is probability of degradation of performance of synchronous system of the network. Considering above, an algorithm has been proposed to reduce the period of re-election of the master signal, considering the attributes and limitations of the MPLS/MPLS-TP and properties of the 1588v2. NS-2 has been used as simulation platform. We have proposed an algorithm based on the probing packets which keep on checking the routes to avoid disruption of the SYNC signal. In the proposed mesh type architecture, three nodes act as masters for three domains and our purpose is to make available SYNC signal to them in various failure conditions. According to interruption of routes, SYNC signal is switched to healthy route.