An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits

Author

Huang, Yi-Chieh ; Wang, Ping-Ying ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

59

Issue

3

fYear

2012

fDate

3/1/2012 12:00:00 AM

Firstpage

148

Lastpage

152

Abstract

An all-digital on-chip jitter tolerance measurement technique for clock/data recovery (CDR) circuits is presented. A 6-Gbps CDR circuit with this proposed technique is realized in a 90-nm CMOS process. The measured jitter tolerance by using the testing equipment and the proposed technique correlate within 13 % in the frequency range of 178 kHz ~ 11.3 MHz. The measured peak-to-peak data and clock jitters are 15.56 and 13.3 ps. The power of the CDR circuit is 44.4 mW at a supply voltage of 1.2 V.

Keywords

CMOS digital integrated circuits; clock and data recovery circuits; integrated circuit testing; jitter; CDR circuits; CMOS process; all-digital on-chip jitter tolerance measurement technique; bit rate 6 Gbit/s; clock jitters; clock-data recovery circuits; frequency 178 kHz to 11.3 MHz; peak-to-peak data; power 44.4 mW; size 90 nm; testing equipment; time 13.3 ps; time 15.56 ps; voltage 1.2 V; Clocks; Field programmable gate arrays; Frequency modulation; Jitter; Noise; Voltage-controlled oscillators; All-digital; clock and data recovery; jitter tolerance;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2012.2184378

Filename

6148266