Spacer Gate Lithography for Reduced Variability Due to Line Edge Roughness

The effect of gate line edge roughness (LER) on bulk-Si MOSFET performance is studied using 3-D device simulations. The benefit of using a spacer (sidewall transfer) gate lithography process to mitigate the effect of LER is assessed, with consideration of source/drain placement and spacer width variation. The simulation results indicate that spacer gate lithography can dramatically reduce LER-induced variation in transistor performance and that variability can be well suppressed with gate-length scaling even if LER does not scale.