Title :
Test sequences to achieve high defect coverage for synchronous sequential circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fDate :
10/1/1998 12:00:00 AM
Abstract :
Test sets that detect each stuck-at fault n>1 times (called n-detection stuck-at test sets) were shown to be effective in achieving high defect coverages. In addition, a pseudofunctional fault model defined before was shown to result in test sets having similar defect coverages. Previous studies of n-detection stuck-at test sets and pseudofunctional test sets were for combinational circuits, In this paper, we study detection stuck-at test sequences and pseudofunctional test sequences for synchronous sequential circuits. Considering stuck-at faults, we propose five definitions of the number of detections achieved by a test sequence. These definitions lead to five different definitions of n-detection stuck at test sequences. We discuss the effects of these definitions on fault-simulation and test-generation procedures and present experimental results for benchmark circuits to evaluate their relative effectiveness. The experimental results indicate the usefulness of the simplest definition in generating test sequences that achieve improved defect coverages. We also describe a pseudofunctional fault model that extends previous definitions. We describe fault-simulation and test-generation methods for this model and give experimental data to evaluate its effectiveness. The results indicate that this model too can be used to generate test sequences with improved defect coverage. Its advantages and disadvantages compared to the n-detection stuck-at model are also considered
Keywords :
automatic test pattern generation; fault simulation; integrated circuit testing; integrated logic circuits; logic testing; sequences; sequential circuits; fault-simulation procedures; high defect coverage; n-detection stuck-at test sets; pseudofunctional fault model; stuck-at faults; synchronous sequential circuits; test sequences; test-generation procedures; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Delay; Electrical fault detection; Fault detection; Sequential analysis; Sequential circuits; Synchronous generators;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on