Design of built-in test generator circuits using width compression

We present a method for designing test generator circuits (TCCs) that incorporate a precomputed test set T_D in the patterns they produce. Our method uses width compression based on the property of d-compatibles as well as compatibles and inverse compatibles and does not require access to a gate-level model of the circuit under test. The TGC consists of a counter, which generates a set of encoded test patterns T_E and a decompression circuit, which consists of simple binary decoders that generate a final sequence containing T_D . We show that partially specified test sets, i.e., those that contain a large number of don´t-cares, lead to more efficient TGCs. These TGCs are applicable to embedded core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results on width compression for the ISCAS´85 benchmark circuits and the full-scan versions of the ISCAS´89 benchmark circuits