DocumentCode
1444205
Title
Compact Layout of On-Chip Transformer
Author
Hsu, Heng-Ming ; Lai, Szu-Han ; Hsu, Chan-Juan
Author_Institution
Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan
Volume
57
Issue
5
fYear
2010
fDate
5/1/2010 12:00:00 AM
Firstpage
1076
Lastpage
1083
Abstract
This study develops a compact layout for an on-chip transformer with both wide range of turn ratios and a high coupling coefficient in a small chip area. Analytical formulas are applied to calculate the self-inductances in the design stage. Therefore, six devices with various turn ratios are designed to verify the proposed layout. All devices are fabricated using foundry 130 nm complementary metal-oxide semiconductor technology. Measurements reveal that the proposed transformer has a wide range of n values (1-5.68) and high coupling k values (0.99-0.48) for a chip area of 1002 ¿m2.
Keywords
CMOS integrated circuits; transformers; compact layout; complementary metal-oxide semiconductor technology; high coupling coefficient; on-chip transformer; self-inductance; size 130 nm; Area measurement; Broadband amplifiers; CMOS technology; Circuit synthesis; Coils; Coupling circuits; Foundries; Geometry; Radio frequency; Semiconductor device measurement; Coupling factor; geometry mean distance; on-chip transformer; turn ratio;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2010.2044280
Filename
5433033
Link To Document