Tagged Repair Techniques for Defect Tolerance in Hybrid Nano/CMOS Architecture

We propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup-table-based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance, and we present theoretical equations to predict the repair capability, including an estimate of the repair cost. The repair techniques are efficient in utilization of spare units and capable of targeting up to 20% defect rates, which is higher than recently reported repair techniques.