On the detectability of CMOS floating gate transistor faults

This paper focuses on the detectability of defects causing the gates of transistors in CMOS integrated circuits to float (open), i.e., on floating gate transistor (FGT) faults. Such faults are known to occur in practice. It is increasingly important to consider their detection to meet high quality requirements for circuits fabricated in deep submicrometer technologies. We focus on the detectability of FGT faults by the standard voltage- and current-based production test strategies that we refer to as static voltage (SV), dynamic voltage (DV), and static current (SC) test strategies. We demonstrate how the behavior of the devices caused by FGT faults depends on two classes of technological and topological parameters: the predictable and unpredictable parameters. We show that an FGT fault can induce abnormal logic values, additional delays, or increased power supply current. We introduce the concept of a detectability interval, i.e., the range of values an unpredictable parameter may assume that one allows for the fault detection using a specific test strategy. We illustrate how the detectability intervals for the SV and DV strategies complement that of the SC strategy. In addition, a new test scheme that results in an increased SC detectability of FGT faults is developed. Finally, we demonstrate the effects of initial trapped charges and the effects of coupling to surrounding metal on the detectability intervals of each of the test strategies