• DocumentCode
    1444576
  • Title

    Clock selection for performance optimization of control-flow intensive behaviors

  • Author

    Khouri, Kamal S. ; Jha, Niraj K.

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • Volume
    20
  • Issue
    1
  • fYear
    2001
  • fDate
    1/1/2001 12:00:00 AM
  • Firstpage
    158
  • Lastpage
    165
  • Abstract
    This paper presents a clock selection algorithm for control-flow intensive behaviors that are characterized by the presence of conditionals and deeply nested loops. Unlike previous papers, which are primarily geared toward data-dominated behaviors, this algorithm examines the effects of branch probabilities and their interaction with allocation constraints. Using examples, we demonstrate, how changing branch probabilities and resource allocation can dramatically affect the optimal clock period, and hence, the performance of the schedule, and show that the interaction of these two factors must also be taken into account when searching for an optimal clock period. We then introduce the clock selection algorithm, which employs a fast critical-path analysis engine that allows it to evaluate what effect different clock periods, branch probabilities, and resource allocations may ultimately have on the performance of the behavior. When evaluating the critical path, we exploit the fact that our target behaviors exhibit locality of execution. We tested our algorithm using a number of benchmarks from various sources. A series of experiments demonstrates that our algorithm is quickly capable of selecting a small set of performance-enhancing clock periods, among which the optimal clock period typically lies. Another experiment demonstrates that the algorithm can adapt to varying resource constraints
  • Keywords
    circuit optimisation; clocks; critical path analysis; hardware description languages; high level synthesis; probability; resource allocation; scheduling; allocation constraints; branch probabilities; clock selection algorithm; control-flow intensive behaviors; critical-path analysis engine; deeply nested loops; locality of execution; optimal clock period; performance optimization; performance-enhancing clock periods; resource allocations; Algorithm design and analysis; Circuit synthesis; Clocks; Engines; Optimization; Performance analysis; Processor scheduling; Resource management; Scheduling algorithm; Testing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.905683
  • Filename
    905683