Frame-level pipelined motion estimation array processor

Author

Kittitornkun, Surin ; Hu, Yu Hen

Author_Institution

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

Volume

11

Issue

2

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

248

Lastpage

251

Abstract

A systolic motion estimation processor (MEP) core architecture implementing the full-search block-matching (FSBM) algorithm is presented. A unique feature of this MEP architecture is its support of frame-level pipelined operation. As such, it is possible to process pixels from consecutive frames without any processor idle time. It is designed so that no data broadcasting operations are required, and achieves 100% fully pipelined computation. It compares favorably with existing MEP architectures in terms of both performance and complexity of architecture

Keywords

VLSI; digital signal processing chips; motion estimation; pipeline processing; search problems; systolic arrays; video signal processing; MEP architecture; VLSI; complexity; frame-level pipelined array processor; full-search block-matching algorithm; performance; pixels rocessing; processor architecture; systolic motion estimation processor; video frame; Acceleration; Broadcasting; Computer architecture; Energy consumption; Motion estimation; Parallel processing; Pipeline processing; Standards development; Timing; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.905990

Filename

905990