An fast lock technique for wide band PLL frequency synthesizer design

This paper presents a wide tuning, low phase noise, and fast locking CMOS integer-N frequency synthesizer with the 1.8V power supply. The frequency synthesizer is designed by using the TSMC 0.18μm CMOS 1P6M technology. It can be used for IEEE 802.1 1ac unlicensed band of Wi-Fi with the frequency ranged from 4.39 GHz to 5.71 GHz for the local oscillator in the RF front-end circuits. The proposed frequency synthesizer consists of a fast-phase-frequency detector charge pump (Fast-PFDCP), a dual mode low-pass loop filter (Dual_Mode_LPF), a voltage control oscillator, an auto-band selection (ABS), an optimum-band selection (OBS), a Lock Detector, and a pulse-swallow divider. This paper achieves the faster locking with the fast phase frequency detector charge pump (Fast-PFDCP) through controlling the 3-bit charge pump scheme with the proposed continuous-time PFD to enhance the locking speed of the proposed PLL. The Dual_Mode_LPF is used to stabilize the loop bandwidth during the locking process. By implementing the proposed design, the locking speed can be enhanced by fifty percent.