Symbol Synchronization for a Class of CPFSK Receiver

This paper describes the design and implementation of Non data aided method for Symbol timing Synchronization for Minimum Shift Keying receiver on Xilinx Virtex 4 FPGA using a feedback structure and lends itself to a simple digital implementation. A new S-curve equation for MSK is obtained by taking interpolation & fractional interval into consideration. Computer simulations are used to assess the synchronizer performance in the presence of AWGN during the transient state and steady state and the results are matching with the practical results. This method works in the presence of fixed carrier phase offset as differential demodulation is used at the receiver. The receiver performance is measured in fixed frequency mode and in frequency hopping mode at 1000 hops/sec for high data rate.