• DocumentCode
    1446205
  • Title

    Fault location in Reed-Muller canonic networks

  • Author

    Kodandapani, K.L.

  • Author_Institution
    University of Regina, Department of Computer Science, Regina, Canada
  • Volume
    124
  • Issue
    4
  • fYear
    1977
  • fDate
    4/1/1977 12:00:00 AM
  • Firstpage
    345
  • Lastpage
    348
  • Abstract
    In the paper, single and multiple-fault locating test sets for Reed-Muller canonic networks are derived. The fault model assumes stuck-at faults at the I/O leads of AND gates, and that an EOR gate under a fault can produce any other function of two inputs other than equivalence. The results in the paper give an insight into the complexity of testing of a class of logic networks.
  • Keywords
    fault location; logic circuits; Reed Muller canonic networks; fault location; logic networks; multiple fault; single fault; test sets; testing complexity;
  • fLanguage
    English
  • Journal_Title
    Electrical Engineers, Proceedings of the Institution of
  • Publisher
    iet
  • ISSN
    0020-3270
  • Type

    jour

  • DOI
    10.1049/piee.1977.0063
  • Filename
    5254008
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1446205