Title :
A 12-b, 60-MSample/s cascaded folding and interpolating ADC
Author :
Vorenkamp, Pieter ; Roovers, Raf
Author_Institution :
Broadcom Corp., Irving, CA, USA
fDate :
12/1/1997 12:00:00 AM
Abstract :
This paper describes the analysis, design, and experimental results of a 12-b, 60-MSample/s analog-to-digital converter (ADC). This ADC is based on a cascaded folding and interpolating architecture. The ADC is optimized for digital telecommunication applications. The cascaded folding and interpolating ADC architecture is introduced, optimizing the overall performance of this converter. The integrated track and hold amplifier enables an SNR>66 dB and a THD<72 dB, measured over an analog input signal bandwidth of 70 MHz. The ADC is realized in a 13-GHz, 1-μm BiCMOS process and measures 7 mm2 , while dissipating 300 mW from a single 5.0 V supply
Keywords :
BiCMOS integrated circuits; analogue-digital conversion; interpolation; sample and hold circuits; 1 micron; 12 bit; 13 GHz; 300 mW; 5.0 V; 70 MHz; BiCMOS process; analog input signal bandwidth; cascaded folding ADC; digital telecommunication applications; integrated track and hold amplifier; interpolating ADC; power dissipation; Analog-digital conversion; Bandwidth; BiCMOS integrated circuits; Costs; Dynamic range; Filters; Frequency; Integrated circuit measurements; Sampling methods; Transceivers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
