A Novel PMOS Data Retention Leakage Power Reduction Design

Leakage power dissipation has become a dominating proportion of the total power dissipation. According to international technology roadmap semiconductor (ITRS), this directly affects the portable battery operated device like mobile phones. A detailed analysis of leakage reduction data retention leakage feedback approaches are discussed in this paper. We here propose a new design data retention scheme which consist PMOS helper transistors which reduces leakage current while saving exact logic state. Based on simulation with inverter chain using 32nm Berkeley predictive technology model, the proposed approach demonstrate that PMOS helper transistors leakage feedback technique reduces considerable amount of leakage in CMOS circuits.