A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors

The multilevel decision feedback equalization (MxDFE) family of detectors provides excellent performance over (1, 7)-coded magnetic recording channels, while being simple in structure. However, the reduced code-rate of 2/3 increases the channel data rate by 50% compared to the user data rate. Although this is not a problem for the write heads because of the reduced bandwidth of the (1, 7) writing signal [compared with (0, k) codes], it becomes an issue at the detector side for high-data-rate applications. We propose a novel interpolation approach for reducing the detector clock rate. Performance simulations of MDFE and M2DFE detectors, carried out over different user densities, channel models, and equalizer configurations, show that the proposed scheme can reduce the detector clock rate to the user rate with negligible impact on performance. We also present a timing recovery scheme for acquisition and tracking of the reduced-rate clock