A high performance reconfigurable flash management framework

In recent years, Solid State Devices (SSDs) have begun to compete with, and replace, mechanical storage devices in terms of reliability and performance. The increased reliability and performance comes mainly from the Flash Translation Layer and flash bus architecture, allowing for multi-chip parallelism. In this paper we present our new FPGA based flash management framework for high performance NAND flash storage systems. Our dynamic scheduler manages flash operations (including chip conflicts) on a shared bus architecture using well-known out-of-order execution techniques. Our FPGA implementation of the flash management framework using synthesizable Verilog enables us to construct a highly concurrent system at a hardware level in the flash controller including the flash translation layer. The results of this highly concurrent system show significant improvement in response time and throughput in terms of read/write operations over existing systems.