Title :
A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface
Author :
Kim, Chulbum ; Ryu, Jinho ; Lee, Taesung ; Kim, Hyunggon ; Lim, Jaewoo ; Jeong, Jaeyong ; Seo, Seonghwan ; Jeon, Hongsoo ; Kim, Bokeun ; Lee, InYoul ; Lee, DooSeop ; Kwak, PanSuk ; Cho, Seongsoon ; Yim, Yongsik ; Cho, Changhyun ; Jeong, Woopyo ; Park, Kwa
Author_Institution :
Semicond. Div., Samsung Electron., Hwasung, South Korea
fDate :
4/1/2012 12:00:00 AM
Abstract :
A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed.
Keywords :
NAND circuits; asynchronous circuits; flash memories; peripheral interfaces; read-only storage; 4-plane arrays; MLC NAND flash memory; asynchronous DDR interface; asynchronous toggle DDR interface; incremental bit line precharge scheme; memory size 64 GByte; monolithic MLC NAND flash; on-chip randomizer; page size; process technology; size 21 nm; soft data readout; Ash; Latches; Layout; Random sequences; Sensors; System-on-a-chip; Timing; Asynchronous double data rate (DDR) interface; NAND flash memory; pseudo differential sensing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2012.2185341
