Title :
1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor
Author :
Karakiewicz, Rafal ; Genov, Roman ; Cauwenberghs, Gert
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
fDate :
4/1/2012 12:00:00 AM
Abstract :
We present a resonant adiabatic mixed-signal 128 × 256 array processor that achieves the energy efficiency of 1.1 TMACS (1012 multiply accumulates per second) per mW of power operating from a 1.6 V DC supply. The 1.9 μm × 9 μm 3T NMOS unit cell with a single-wire pitch multiplexed bit/compute line provides charge-conserving 1b-1b multiplication and single-node charge-domain analog accumulation. A stochastic data modulation scheme minimizes on-chip capacitance variability maintaining sinusoidal clock oscillations near resonance.
Keywords :
CMOS integrated circuits; mixed analogue-digital integrated circuits; stochastic processes; CMOS adiabatic computational array; NMOS unit cell; TMACS; a single-wire pitch multiplexed bit-compute line; charge-conserving 1b-1b multiplication; energy efficiency; on-chip capacitance variability; resonant adiabatic mixed-signal array processor; single-node charge-domain analog accumulation; sinusoidal clock oscillations; stochastic data modulation scheme; stochastic resonant charge-recycling array processor; voltage 1.6 V; Arrays; Capacitance; Logic gates; Microprocessors; Random access memory; Transistors; Adiabatic; charge-recycling; matrix-vector multiplication; mixed-signal and charge-mode;
Journal_Title :
Sensors Journal, IEEE
DOI :
10.1109/JSEN.2011.2113393
