Accelerated quasi-DC method and circuit for measuring the gate-drain coupling capacitance for devices within a CMOS process technology

An accelerated measurement scheme is presented which measures the gate-drain capacitance C_gd. The scheme can be used to measure C_gd as a function of bias voltage. The test structure consists of two MOS transistors connected together by their gates. One transistor is used to couple charge to the floating gate node, while the other is used to sense the amount of gate-drain charge coupling. Using the basic structure a circuit topology is derived which enables one to measure C_gd in less than 100 ms. The various measurement errors are also discussed