Harvest rate of reconfigurable pipelines

Author

Shi, Weiping ; Chang, Ming Feng ; Fuchs, W. Kent

Author_Institution

Dept. of Comput. Sci., North Texas Univ., Denton, TX, USA

Volume

45

Issue

10

fYear

1996

fDate

10/1/1996 12:00:00 AM

Firstpage

1200

Lastpage

1203

Abstract

For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. The authors give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: there are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the “shifting” reconfiguration as weighted chains in a partial ordered set, they prove when n=θ(m), the harvest rate is between 34% and 72%

Keywords

arrays; multistage interconnection networks; pipeline processing; reconfigurable architectures; defect-free processors; harvest rate; independent probability; partial ordered set; reconfigurable architecture; reconfigurable pipelines; shifting reconfiguration; spare wires; topology; weighted chains; Computer science; Equations; Parallel architectures; Pipelines; Reconfigurable architectures; Shape; Supercomputers; Topology; Very large scale integration; Wires;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.543713

Filename

543713