• DocumentCode
    14484
  • Title

    Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

  • Author

    Khandelwal, Sourabh ; Agarwal, Harshit ; Duarte, Juan Pablo ; Kaiman Chan ; Dey, Sagnik ; Chauhan, Yogesh Singh ; Chenming Hu

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, Berkeley, CA, USA
  • Volume
    34
  • Issue
    8
  • fYear
    2015
  • fDate
    Aug. 2015
  • Firstpage
    1291
  • Lastpage
    1294
  • Abstract
    We enhance the capability of industry standard compact model BSIM6 to model the parasitic current Iedge at the shallow trench isolation edge. Accurate, efficient, and scalable model for Iedge is developed by finding the key differences between Iedge and main device drain current (Imain). It is found that Iedge has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to Imain. These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.
  • Keywords
    analogue circuits; circuit simulation; BSIM6; STI edge parasitic current; circuit simulations; industry standard compact model; shallow trench isolation edge; Computational modeling; Data models; Integrated circuit modeling; Materials; Mathematical model; Semiconductor device modeling; Temperature measurement; Analog technology; BSIM6; Compact Models; Parasitic Currents; STI Edge Effects; compact models; parasitic currents; shallow trench isolation (STI) edge effects;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2015.2419626
  • Filename
    7079473