DocumentCode :
144886
Title :
100Gbit/s FEC for OTN protocol: Design architecture and implementation results
Author :
Salvador, Arley ; Carvalho, Diego ; Nakandakare, Cleber ; Mobilon, Eduardo ; de Oliveira, Jose Carlos ; Arantes, Dalton S.
Author_Institution :
Convergence Network Dept., CPqD R&D Center in Telecom, Campinas, Brazil
fYear :
2014
fDate :
17-20 Aug. 2014
Firstpage :
1
Lastpage :
5
Abstract :
Error correcting codes are widely used in telecommunication systems in order to increase the robustness of the system. With the exponential growth of the data communication world, the architecture of such systems have had to adapt to allow for improved channel capacity and reduced transmission costs. The architecture and hardware implementation challenges of the Reed Solomon RS(255, 239) for OTN networks in 100Gbit/s is presented.
Keywords :
Reed-Solomon codes; channel capacity; forward error correction; optical fibre networks; OTN networks; Reed Solomon RS; bit rate 100 Gbit/s; channel capacity; data communication; error correcting codes; reduced transmission costs; telecommunication systems; Clocks; Computer architecture; Decoding; Field programmable gate arrays; Forward error correction; Polynomials; Reed-Solomon codes; 100 Gbit/s; FEC; OTN; Reed Solomon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Telecommunications Symposium (ITS), 2014 International
Conference_Location :
Sao Paulo
Type :
conf
DOI :
10.1109/ITS.2014.6947951
Filename :
6947951
Link To Document :
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