A 200-MSPS 6-bit flash ADC in 0.6-μm CMOS

Author

Dalton, Declan ; Spalding, George ; Reyhani, Hooman ; Murphy, Tim ; Deevy, Ken ; Walsh, Mairtin ; Griffin, Patrick

Author_Institution

Analog Devices Inc., Limerick, Ireland

Volume

45

Issue

11

fYear

1998

fDate

11/1/1998 12:00:00 AM

Firstpage

1433

Lastpage

1444

Abstract

This paper describes a 6-bit flash analog-to-digital converter (ADC) which performs the sampling function in a partial-response, maximum-likelihood (PRML) disk drive read channel. It operates with sampling frequencies up to 200 MSPS and achieves an effective number of bits (ENOB) of 5.5 bits with F_in=50 MHz and 5.0 bits at F_in=100 MHz. It consumes 380 mW at 5 V and occupies 2.7 mm ². Other features include a bit-error rate of <1e-10 and a programmable nonlinear transfer function

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); disc drives; maximum likelihood detection; partial response channels; 0.6 micron; 100 MHz; 380 mW; 5 V; 50 MHz; 6 bit; CMOS; ENOB; bit-error rate; disk drive read channel; effective number of bits; flash ADC; partial-response maximum-likelihood channel; programmable nonlinear transfer function; sampling function; Bandwidth; Bit error rate; Circuits; Clocks; Delay; Maximum likelihood detection; Sampling methods; Signal processing; Signal sampling; Timing;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.735355

Filename

735355