• DocumentCode
    1448907
  • Title

    Three-dimensional computational pipelining with minimal latency and maximum throughput for L-U factorization

  • Author

    Paul, JoAnn M. ; Mickle, Marlin H.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
  • Volume
    45
  • Issue
    11
  • fYear
    1998
  • fDate
    11/1/1998 12:00:00 AM
  • Firstpage
    1465
  • Lastpage
    1475
  • Abstract
    A three-dimensional (3-D) wavefront array with minimal computation time (latency) of 2n-2 cycles for an n*n matrix and minimal block pipelining period of one is introduced and compared to existing two-dimensional (2-D) systolic array architectures for L-U factorization. An optimal processor-time product of (1/3)n3 with cycles defined computationally by two operations is obtained when successive problem instances are considered. The 3-D architecture is extensible and scalable, is cycle invariant (all respects), has minimal node complexity of two arithmetic operations per cycle, has unidirectional data forwarding in three dimensions, has 100% utilization of processing elements for successive inputs, and has a cycle-invariant one-to-one correspondence between input/output ports and input/output matrix elements
  • Keywords
    matrix decomposition; pipeline processing; systolic arrays; 3D wavefront array; L-U factorization; arithmetic operations; computation time; cycle invariant; cycle-invariant one-to-one correspondence; input/output matrix elements; input/output ports; latency; minimal node complexity; optimal processor-time product; processing elements; successive inputs; successive problem instances; systolic array architectures; three-dimensional computational pipelining; throughput; unidirectional data forwarding; Bandwidth; Circuits; Computer architecture; Delay; Pipeline processing; Signal processing algorithms; Systolic arrays; Throughput; Two dimensional displays; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/82.735358
  • Filename
    735358