π-heterostructure field effect transistors for VLSI applications

A quantum-well heterostructure field effect transistor (HFET) with a p⁺ gate and fairly heavily doped p-type buffer is described. This device is called a π-HFET, meaning p-type insulated gate HFET. The effective barrier height in a π-HFET is considerably larger than in other compound semiconductor FETs, and the gate current at maximum gate voltage swing can be made negligible, even at room temperature. Based on the tradeoff between the noise margin and speed, 0.7 and 1.5 V are proposed as the minimum power supply voltages for the direct-coupled FET logic at 77 and 300 K, respectively. Calculations demonstrate that this π-HFET technology can meet all requirements for VLSI applications, and that high electron velocity and mobility in π-HFETs lead to an increase in speed of output drivers by a factor of four at 77 K and a factor of 10 at 300 K (compared to Si NMOS which is faster than CMOS). The full advantages of π-HFET technology can be realized only on a submicrometer scale, where source and drain series resistances play a dominant role in determining the noise margin