• DocumentCode
    1449668
  • Title

    A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling

  • Author

    Adams, Rene ; Nguyen, K. Quang

  • Author_Institution
    Analog Devices Inc., Wilmington, MA
  • Volume
    33
  • Issue
    12
  • fYear
    1998
  • fDate
    12/1/1998 12:00:00 AM
  • Firstpage
    1871
  • Lastpage
    1878
  • Abstract
    A sigma-delta digital/analog converter implemented in 0.6-μ CMOS uses a 6-bit modulator together with a segmented noise-shaped scrambling scheme to achieve 113-dB A-weighted dynamic range over a 20-kHz bandwidth. A continuous-time output stage is used to achieve high signal-to-noise ratio in a 9.1-mm2 die area. The output stage uses a dual return-to-zero circuit that eliminates errors caused by intersymbol interference
  • Keywords
    CMOS integrated circuits; continuous time systems; digital-analogue conversion; integrated circuit noise; intersymbol interference; sigma-delta modulation; 0.6 micron; 20 kHz; 6 bit; CMOS chip; continuous-time output stage; dual return-to-zero circuit; dynamic range; intersymbol interference; modulator; oversampling DAC; segmented noise shaped scrambling; sigma-delta digital/analog converter; signal-to-noise ratio; Active filters; Analog-digital conversion; Capacitance; Circuit noise; Clocks; Digital modulation; Dynamic range; Inverters; Jitter; Signal to noise ratio;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.735526
  • Filename
    735526
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1449668