Title :
An analog background calibration technique for time-interleaved analog-to-digital converters
Author :
Dyer, Kenneth C. ; Fu, Daihong ; Lewis, Stephen H. ; Hurst, Paul J.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
fDate :
12/1/1998 12:00:00 AM
Abstract :
Analog background calibration using adaptive signal processing, an extra channel, and mixed signal integrators matches the offsets and gains of time-interleaved channels in a 10-b 40-Msample/s pipelined analog-to-digital converter. With monolithic background calibration, the peak signal-to-noise-and-distortion ratio is 58 dR, and power dissipation is 650 mW from 5 V. The active area is 47 mm2 in 1 μm CMOS
Keywords :
CMOS integrated circuits; adaptive signal processing; analogue-digital conversion; calibration; integrating circuits; 1 micron; 10 bit; 5 V; 650 mW; CMOS technology; adaptive signal processing; analog background calibration technique; analog-to-digital converters; mixed signal integrators; pipelined ADC; time-interleaved ADC; Adaptive signal processing; Adaptive systems; Analog-digital conversion; Calibration; Power dissipation; Sampling methods; Signal processing; Signal sampling; Signal to noise ratio; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
