Title :
A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture
Author :
Fukaishi, Muneo ; Nakamura, Kazuyuki ; Sato, Masaharu ; Tsutsui, Yutaka ; Kishi, Syuji ; Yotsuyanagi, Michio
Author_Institution :
System ULSI Res. Lab., NEC Corp., Kanagawa, Japan
fDate :
12/1/1998 12:00:00 AM
Abstract :
A single-chip 1.25-Gb/s 32:1, 1:32 transceiver, as specified in the emerging American National Standards Institute fiber channel standard, has been developed using 0.25-μm CMOS technology. Newly developed features contributing to the achievement of 4.25-Gb/s operations include: 1) an asynchronous tree-type 1:8 demultiplexer, 2) an 8-10 bit parallel-to-parallel frequency conversion circuit, and 3) comma detection and word alignment logic. The transceiver consumes 600 mW in 4.25-Gb/s operations with a 2.5 V supply. This design helps achieve higher speed operations and only half the power dissipation of the fastest previously reported CMOS fiber channel design that includes an 8B10B encoder and a 10B8B decoder
Keywords :
CMOS digital integrated circuits; demultiplexing equipment; optical communication equipment; optical fibre communication; optical frequency conversion; transceivers; 0.25 micron; 10B8B decoder; 2.5 V; 4.25 Gbit/s; 600 mW; 8 to 10 bit; 8B10B encoder; CMOS fiber channel transceiver; asynchronous tree-type demultiplexer; comma detection; parallel-to-parallel frequency conversion circuit; power dissipation; single chip device; word alignment logic; CMOS logic circuits; CMOS technology; Clocks; Frequency conversion; Inverters; Laboratories; Logic circuits; Optical fiber communication; Standards development; Transceivers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
