DocumentCode
1450270
Title
Tunneling through ultrathin GaAs n++-p++-n ++ barrier grown by molecular layer epitaxy
Author
Liu, Yong-Xun ; Plotka, Piotr ; Suto, Ken ; Oyama, Yutaka ; Nishizawa, Jun-ichi
Author_Institution
Dept. of Mater. Sci. & Eng., Tohoku Univ., Sendai, Japan
Volume
45
Issue
12
fYear
1998
fDate
12/1/1998 12:00:00 AM
Firstpage
2551
Lastpage
2554
Abstract
The I-V characteristics of ultrathin GaAs n++-p++ -n++ barrier structures with a 45 Å thick p++ layer grown by molecular layer epitaxy (MLE) have been measured at room temperature and 77 K. The tunneling probability for this structure has been calculated as a function of effective tunneling width. It was found that good agreement between experiment and calculation is obtained when the effective tunneling width is assumed to be 75 Å, which is much smaller than the depletion width about 190 Å measured by C-V method. This fact indicates that the depletion width approximation cannot be used to measure the exact tunneling width for ultrathin barrier devices
Keywords
III-V semiconductors; gallium arsenide; molecular beam epitaxial growth; semiconductor epitaxial layers; semiconductor junctions; tunnelling; GaAs; I-V characteristics; depletion width approximation; molecular layer epitaxy; tunneling; ultrathin GaAs n++-p++-n++ barrier; Doping; Electrons; Epitaxial growth; Gallium arsenide; Gold; Maximum likelihood estimation; Probability; Temperature measurement; Thickness measurement; Tunneling;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.735735
Filename
735735
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