DocumentCode :
1450535
Title :
A 31 ns Random Cycle VCAT-Based 4F ^{2} DRAM With Manufacturability and Enhanced Cell Efficiency
Author :
Song, Ki-Whan ; Kim, Jin-Young ; Yoon, Jae-Man ; Kim, Sua ; Kim, Huijung ; Chung, Hyun-Woo ; Kim, Hyungi ; Kim, Kanguk ; Park, Hwan-Wook ; Hyun Chul Kang ; Tak, Nam-kyun ; Park, Dukha ; Kim, Woo-Seop ; Lee, Yeong-Taek ; Yong Chul Oh ; Jin, Gyo-Young ; Yoo
Author_Institution :
Memory Div., Samsung Electron. Co., Hwasung, South Korea
Volume :
45
Issue :
4
fYear :
2010
fDate :
4/1/2010 12:00:00 AM
Firstpage :
880
Lastpage :
888
Abstract :
A functional 4F2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the conventional recessed channel access transistor (RCAT). A new design methodology has been applied to accommodate 4F2 cell array, achieving both high performance and manufacturability. Especially, core block restructuring, word line (WL) strapping and hybrid bit line (BL) sense-amplifier (SA) scheme play an important role for enhancing AC performance and cell efficiency. A 50 Mb test chip was fabricated by 80 nm design rule and the measured random cycle time (tRC) and read latency (tRCD) are 31 ns and 8 ns, respectively. The median retention time for 88 Kb sample array is about 30 s at 90°C under dynamic operations. The core array size is reduced by 29% compared with conventional 6F2 DRAM.
Keywords :
DRAM chips; capacitors; transistors; DRAM; cell array; core block restructuring; hybrid bit line sense-amplifier scheme; random cycle time; read latency time; recessed channel access transistor; size 80 nm; stack capacitor; temperature 90 C; time 31 ns; time 8 ns; vertical channel access transistor; word line strapping; Capacitance; Capacitors; Coupling circuits; Dielectric materials; Doping; Dry etching; Joining processes; Random access memory; Scalability; Wet etching; 4F $^{2}$; DRAM; cell efficiency; core architecture; hybrid sense-amplifier (SA); stack capacitor; surrounding-gate vertical channel access transistor (VCAT);
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2010.2040229
Filename :
5437489
Link To Document :
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