Title :
A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13
CMOS Technology
Author :
Yu, Jianjun ; Dai, Fa Foster ; Jaeger, Richard C.
Author_Institution :
Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
fDate :
4/1/2010 12:00:00 AM
Abstract :
A 12-bit Vernier ring time-to-digital converter (TDC) with time resolution of 8 ps for digital-phase-locked-loops (DPLL) is presented. This novel Vernier ring TDC places the Vernier delay cells and arbiters in a ring format and reuses them for the measurement of the input time interval. The proposed TDC thus achieves large detectable range, fine time resolution, small die size and low power consumption simultaneously. A pre-logic unit is developed to measure both positive and negative phase errors for DPLL applications. The TDC achieves a large detectable range of 12 bits with core area of 0.75 Ã 0.35 mm2 in a 0.13 μm CMOS technology. The total power consumption for the entire TDC chip is only 7.5 mW with a 1.5 V power supply, while operating at a clock frequency of 15 MSPS.
Keywords :
CMOS integrated circuits; digital phase locked loops; 12-bit vernier ring time-to-digital converter; CMOS technology; DPLL; core area; digital-phase-locked-loop; fine time resolution; input time interval; large detectable range; power 7.5 mW; power consumption; pre-logic unit; size 0.13 μm; small die size; vernier delay cells; vernier ring TDC; voltage 1.5 V; CMOS technology; Circuit noise; Digital filters; Energy consumption; Frequency; Phase locked loops; Phase measurement; Phase noise; Quantization; Time measurement; Digital phase locked loop (DPLL); Vernier; frequency synthesis; time and phase measurement; time-to-digital converter (TDC);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2010.2040306