A Fractional-N PLL for Multiband (0.8–6 GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency Δ-Σ Modulator

Author

Jian, Heng-Yu ; Xu, Zhiwei ; Wu, Yi-Cheng ; Chang, Mau-Chung Frank

Author_Institution

Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA

Volume

45

Issue

4

fYear

2010

fDate

4/1/2010 12:00:00 AM

Firstpage

768

Lastpage

780

Abstract

A compact, low power and global-mismatch-tolerant 0.8-6 GHz fractional-N PLL is designed to cover IEEE 802.11abg, PCS/DCS and cellular bands. Two new techniques are proposed to cancel the in-band quantization noise and fractional spurs. Firstly, a second order binary-weighted digital/analog differentiator (DAD) is utilized to enable the second order mismatch shaping and reduce the quantization noise by 25 dB, along with advantages of compact circuit implementation with smaller routing area and less power consumption over those of dynamic element matching (DEM) based counterparts. Secondly, mechanisms causing fractional spurs are also identified and a third order offset-frequency delta-sigma (Δ-Σ) modulator is devised to decrease the in-band spurs by 20 dB in simulation and 8 dB in present single-ended circuit implementation.

Keywords

delta-sigma modulation; phase locked loops; quantisation (signal); wireless LAN; IEEE 802.11abg; PCS/DCS; bandwidth 0.8 GHz to 6 GHz; binary-weighted D/A differentiator; cellular bands; compact circuit implementation; delta-sigma modulator; digital/analog differentiator; dynamic element matching; fractional spurs; fractional-N PLL; global mismatch tolerant; in-band quantization noise; multiband communications; offset-frequency Δ-Σ modulator; second order mismatch shaping; 1f noise; Circuit noise; Distributed control; Noise cancellation; Noise reduction; Noise shaping; Personal communication networks; Phase locked loops; Quantization; Routing; Fractional- $N$; binary-weighted digital-analog differentiator (DAD); delta-sigma modulation; digital-analog conversion; fractional spurs; mismatch shaping; multiband frequency synthesizer; offset-frequency delta-sigma $(Delta {hbox{-}} Sigma)$ modulator; phase-locked loop (PLL); quantization noise;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2010.2040232

Filename

5437492