Title :
A novel delay-locked loop based CMOS clock multiplier
Author :
Birru, Dagnachew
Author_Institution :
Digital VLSI Group, Philips Res. Lab., Eindhoven, Netherlands
fDate :
11/1/1998 12:00:00 AM
Abstract :
On-chip clock-rate multiplication is usually achieved using a phase-locked-loop (PLL) circuit. However, integration of such an analog-intensive and noise-sensitive circuit with a digital circuit constitutes a major challenge. As an alternative solution, this paper proposes an attractive fully integratable delay-locked loop (DLL) based clock-rate multiplier by a modest integer factor. The implementation of the total circuit in the standard digital CMOS process is extremely simple and robust. The circuit can be part of a standard digital cell library and can easily be integrated with digital circuits. Simulation and experimental results are provided to evaluate the performance of the proposed circuit
Keywords :
CMOS digital integrated circuits; clocks; delay lock loops; multiplying circuits; timing circuits; DLL; clock-rate multiplier; delay-locked loop based CMOS clock multiplier; digital CMOS; digital circuits; integratable delay-locked loop; on-chip clock-rate multiplication; performance; CMOS process; CMOS technology; Clocks; Delay; Digital circuits; Inverters; Logic; Oscillators; Phase locked loops; Software libraries;
Journal_Title :
Consumer Electronics, IEEE Transactions on
