A novel delay-locked loop based CMOS clock multiplier

On-chip clock-rate multiplication is usually achieved using a phase-locked-loop (PLL) circuit. However, integration of such an analog-intensive and noise-sensitive circuit with a digital circuit constitutes a major challenge. As an alternative solution, this paper proposes an attractive fully integratable delay-locked loop (DLL) based clock-rate multiplier by a modest integer factor. The implementation of the total circuit in the standard digital CMOS process is extremely simple and robust. The circuit can be part of a standard digital cell library and can easily be integrated with digital circuits. Simulation and experimental results are provided to evaluate the performance of the proposed circuit