Title :
Thickness limitations of SiO2 gate dielectrics for MOS ULSI
Author :
Wright, Peter J. ; Saraswat, Krishna C.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
fDate :
8/1/1990 12:00:00 AM
Abstract :
The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined. Leakage current has been found to be a greater problem for static logic than for dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations, and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si3N 4 has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; integrated logic circuits; semiconductor device models; silicon compounds; 2 to 3 nm; CMOS; MISFET; MOS ULSI; MOSFET performance; Si3N4 gate dielectrics; SiO2 gate dielectrics; drain current characteristics; drain design; dynamic logic; gate leakage current; limits on gate oxide thickness; minimum oxide thickness; scaling; static logic; CMOS logic circuits; Dielectrics; Gate leakage; Leakage current; Logic circuits; MOSFET circuits; Semiconductor process modeling; Tunneling; Ultra large scale integration; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
