Title :
Modeling of delay variability due to random dopant fluctuation in nano-scale CMOS inverter
Author_Institution :
Key Lab. for RF Circuits & Syst. of Minist. of Educ., Hangzhou Dianzi Univ., Hangzhou, China
Abstract :
As CMOS technology is scaled down to nanometer feature size, process variations such as random dopant fluctuation (RDF) are crucial to the performance of integrated devices and circuits because of its effect on threshold voltage VT. Therefore, it is urgent to model their behavior and predict their characteristics in early IC design stage. In this paper, a model for estimation of delay variability for nano-scale CMOS inverter due to RDF is proposed applying an improved average drain current law. The standard deviation is derived based on propagation of variation from analytical expression of delay. The presented model is verified and compared to Monte Carlo simulations with HSPICE using industrial 65nm technology. The derived model is very simple and effective to predict delay variation for nano-scale CMOS inverter.
Keywords :
CMOS integrated circuits; Monte Carlo methods; SPICE; integrated circuit design; integrated circuit modelling; invertors; nanotechnology; CMOS inverter; HSPICE; IC design; Monte Carlo simulations; delay variability modeling; integrated circuits; integrated devices; nanometer feature size; random dopant fluctuation; size 65 nm; threshold voltage; delay model; nano-scale MOSFET; process variation; random dopant fluctuation;
Conference_Titel :
Information Science, Electronics and Electrical Engineering (ISEEE), 2014 International Conference on
Conference_Location :
Sapporo
Print_ISBN :
978-1-4799-3196-5
DOI :
10.1109/InfoSEEE.2014.6948090
