Modeling of delay variability due to random dopant fluctuation in nano-scale CMOS inverter

As CMOS technology is scaled down to nanometer feature size, process variations such as random dopant fluctuation (RDF) are crucial to the performance of integrated devices and circuits because of its effect on threshold voltage V_T. Therefore, it is urgent to model their behavior and predict their characteristics in early IC design stage. In this paper, a model for estimation of delay variability for nano-scale CMOS inverter due to RDF is proposed applying an improved average drain current law. The standard deviation is derived based on propagation of variation from analytical expression of delay. The presented model is verified and compared to Monte Carlo simulations with HSPICE using industrial 65nm technology. The derived model is very simple and effective to predict delay variation for nano-scale CMOS inverter.