Title :
Input polling arbitration mechanism for a gigabit packet switch
Author :
Son, J.W. ; Oh, Y.Y. ; Lee, H.T. ; Lee, J.Y. ; Lee, S.B.
Author_Institution :
Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
fDate :
10/24/1996 12:00:00 AM
Abstract :
Two head of line (HOL) packet arbitration mechanisms in an input buffered gigabit packet switch are proposed. These mechanisms have significant advantages in simple implementation while their performances still remain at acceptable levels
Keywords :
digital communication; packet switching; protocols; gigabit packet switch; head of line arbitration mechanism; input buffered packet switch; input polling arbitration mechanism;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961368
