DocumentCode
1451287
Title
Efficient synthesis algorithm for low-power ASIC design
Author
Lee, Hae-Dong ; Lee, Jong-Suk ; Hyun, Min-Ho ; Hwang, Sun-Young
Author_Institution
Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea
Volume
32
Issue
22
fYear
1996
fDate
10/24/1996 12:00:00 AM
Firstpage
2060
Lastpage
2062
Abstract
The authors propose an efficient synthesis algorithm for the synthesis of RT-level hardware with low power consumption. The proposed algorithm minimises the overall power consumption of generated datapath by reducing spurious operations. Experimental results for several benchmark circuits under various synthesis constraints show the efficiency of the proposed algorithm
Keywords
application specific integrated circuits; circuit CAD; high level synthesis; integrated circuit design; RT-level hardware; low power consumption; low-power ASIC design; synthesis algorithm;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19961403
Filename
543814
Link To Document