Title :
Inverter delay modelling for submicrometre CMOS process
Author :
Daga, J.-M. ; Turgis, S. ; Auvergne, D.
Author_Institution :
LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fDate :
10/24/1996 12:00:00 AM
Abstract :
The authors present an improved macro-model for the delay of CMOS inverters for a submicrometre process. This model includes input-to-output coupling capacitance, short circuit current and input slope effects. Validations are obtained by comparing simulated (HSPICE level 6, for a 0.7 μm process) and calculated values of delays for various conditions of input control and driving ability ratio between the short circuiting and the driving transistors
Keywords :
CMOS logic circuits; SPICE; delays; integrated circuit modelling; logic gates; 0.7 micron; CMOS inverter; HSPICE simulation; delay; driving ability ratio; input control; input slope; input-to-output coupling capacitance; macro-model; short circuit current; submicrometre process;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961394
