Title :
Low-powered 2.1 μs binary delay line in radiation hard SOI-BiCMOS technology
Author_Institution :
Interuniv. Inst. for High Energies, Free Univ. Brussels, Belgium
fDate :
10/24/1996 12:00:00 AM
Abstract :
The requirements of the presented binary delay line are low power, small area and minimum delay of 2 μs at a clock rate of 40 MHz. This binary delay line is implemented in 0.8 μm radiation hard SOI-SIMOX BiCMOS-PJFET technology of DMILL and consumes <450 μW/channel for a design with four channels and is part of a larger read-out chip for capacitive detectors
Keywords :
BiCMOS analogue integrated circuits; SIMOX; delay lines; radiation hardening (electronics); 0.8 micron; 2.1 mus; 40 MHz; 450 muW; DMILL; capacitive detector; low-power binary delay line; radiation hard SOI-SIMOX BiCMOS-PJFET technology; read-out chip;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961399
